The present invention relates to a semiconductor memory device.
The memory capacity of a dynamic random access memory (DRAM) is increasing significantly, and DRAMs having a large capacity of 64 kbit are already currently mass-produced. However, in a 64-kbit RAM of this type, since the power supply voltage is lowered from 12 V to 5 V, the amount of storage charge is reduced. When a memory cell of such a 64-kbit RAM stores a voltage lower than the power supply voltage by a threshold voltage of the cell as in the case of an ordinary RAM of small memory capacity, the loss in the storage charge in the cell amounts to about 20% due to the power supply voltage of 5 V. Such a loss results in degradation of the dynamic memory cell characteristics. For example, when the storage charge decreases, the memory is more easily subject to so-called soft error which is caused by .alpha.-particles. Soft error is a phenomenon in which .alpha.-particles produced in the process of radioactive decay of uranium or thorium in a package or the like enter into the semiconductor substrate to generate electrons therein, and the electrons are trapped by the depletion layer and temporarily render the memory cell defective. In order to prevent such a soft error, it is preferable to increase the storage charge of the memory cell.
A thinner dielectric film may be used to increase the capacitance of the memory cell and to obtain the desired amount of the storage charge. However, this renders the manufacture of the device difficult, lowers the withstand voltage of the resultant device, and also lowers the manufacturing yield of the devices.
In order to prevent a loss in the storage charge, it is also conceivable to increase the potential on the bit line and to hold a voltage equivalent to the power supply voltage in the memory cell.
FIG. 1 shows a circuit diagram of part of a conventional memory device having a pull-up function for boosting the potential on a bit line. The memory device has memory cells MC1 to MCN which are commonly connected to a bit line BL and which are respectively coupled to word lines WL1 to WLN, a pull-up circuit 2, and a sense amplifier 4 which is coupled to the bit line BL and which detects and amplifies the data transmitted on the bit line BL. The pull-up circuit 2 has a MOS transistor TR1 coupled between a power supply terminal VC and the bit line BL, a MOS transistor TR2 coupled between a node N1 or the gate of the MOS transistor TR1 and the bit line BL, and a capacitor C1, one end of which is connected to the node N1 and the other end of which is connected to receive a pull-up signal PS1.
The operation of the memory device shown in FIG. 1 will now be described with reference to FIGS. 2(A) to 2(C). Prior to readout of data from a memory cell, the bit line BL is precharged to a power supply voltage level VCC, as shown in FIG. 2(A). In this case, the potential at the node N1 is set to a potential level which is lower than the power supply voltage VCC by the threshold voltage of the MOS transistor TR2, as shown in FIG. 2(B). When one of the memory cells MC1 to MCN is selected thereafter, the potential on the bit line BL changes in accordance with the data of the selected memory cell. When the data stored in the selected memory cell is "1", for example, the potential on the bit line BL is kept at a potential level slightly lower than the power supply voltage, as indicated by the solid curve shown in FIG. 2(A). On the other hand, when this data is "0", the potential on the bit line BL is lowered to 0 V, as indicated by the broken curve shown in FIG. 2(A). The potential on the bit line BL is then detected and amplified by the sense amplifier 4.
When the pull-up signal PS1 goes high thereafter, as shown in FIG. 2(C), the potential at the node N1 is pulled up to a potential level which is sufficiently higher than the power supply voltage VCC, as indicated by the solid curve shown in FIG. 2(B). Then, the MOS transistor TR1 is completely turned on, and the potential on the bit line BL is kept at the power supply voltage level as shown in FIG. 2(A). The memory cell stores the same amount of storage charge as that in the initial state.
In the memory device shown in FIG. 1, the potential on the bit line BL is held at the power supply voltage level VCC, as has been described earlier. However, when a memory device of a large memory capacity is formed to have a high density, the capacitance of the storage capacitor of each memory cell is made small, so that a sufficient storage charge can not be stored within this memory cell. In order to obtain a satisfactory storage charge, the potential on the bit line BL must be set higher than the power supply voltage level VCC, and a still higher voltage must be applied across the storage capacitor of the memory cell. For achieving this purpose, a pull-up capacitor C2 may be connected to the bit line BL as shown in FIG. 3, and a pull-up signal PS2 is applied to the capacitor C2 at a proper timing, so that the potential on the bit line BL may be set at a level higher than the power supply voltage level. However, with this method, the capacitance on the bit line BL is inadvertently increased. Accordingly, the logic level of the data read out from one of the memory cells MC1 to MCN onto the bit line BL is lowered, resulting in an impractical memory device.